array architecture
英 [əˈreɪ ˈɑːkɪtektʃə(r)]
美 [əˈreɪ ˈɑːrkɪtektʃər]
网络 数组结构; 陈列结构; 阵列架构
双语例句
- On this basis, complex operation is available with a two-stage array architecture.
复数运算由包含四个区域的两层阵列完成，并进行了光学实验。 - Optimized Parallelization of Loop Nests for Multi-core Array Architecture
基于多核阵列体系结构的嵌套循环并行优化 - Study of array modular architecture integration magnetics in four-phase voltage regulator module
阵列式积木结构集成磁件在四相VRM中的应用研究 - A divided memory cell array architecture and high speed hierarchical sense amplifiers are employed in the design to optimize the structure of the circuit.
通过采用存储阵列的分块、敏感放大器的分级等技术，对电路的结构进行了优化。 - Firstly, the frame of FPGA is constituted through analyzing the commercial FPGA devices, with the LUT-based logic cells and symmetrical array routing architecture adopted.
通过研究商用FPGA的特性制定了FPGA总体结构：逻辑单元采用基于LUT的单元，布线结构为对称阵列结构。 - First, the low testing power DFT solution& Scan Array architecture are presented. In the Scan Array, the inserted wrapper and paralleled leaf scan chain reduce the testing power as low as the power dissipation in the normal working mode.
首先，从优化测试功耗的角度出发提出了扫描阵列结构，通过加入Wrapper测试控制结构以及构建并行化的分支扫描链，有效地将测试功耗降低到与正常工作功耗相当的量级。 - An improved cross-interference iterative decoding algorithm for multiple input multiple output ( MIMO) structure was proposed to reduce the interference among users employing the same resource in generalized distributed antenna array architecture of beyond 3G ( B3G) system.
针对超3代（B3G）系统中广义分布式天线阵的架构，提出了适用于多个多天线阵中多输入多输出（MIMO）结构的交叉迭代检测译码算法。 - There are simple control signal of inner unit and simple operation in the array architecture. Therefore there aren't feedback signal and complicated control signal.
结构的设计采用了脉动阵列，并且阵列单元模块的内部结构控制信号和运算过程简单，不存在输出信号反馈和多种信号综合控制的情况。 - This paper presents a kind of systolic array architecture which is used to realize BP algorithm. It designs a characters recognition system in FPGA based on this systolic array architecture.
提出了一种用于实现BP神经网络的串行输入串行输出的脉动阵列结构，在FPGA上实现了基于该阵列结构的用于进行A-Z的印刷体字符识别系统。 - This paper presents a tri-stage memory array architecture to solve the problem, which can accomplish the arbitrary high-speed packet buffer theoretically.
提出一种新型的三级存储阵列结构可以成功解决数据包存储器的容量和带宽问题，理论上可以实现任意高速数据包的缓存。 - A new approach is presented of the eigen-structure subspace algorithms, the problem of ambiguous estimation in the original algorithm is solved and array architecture is optimized.
提出了改进的特征结构子空间算法，采用二维联合估计方法，解决了原算法存在的角度估计模糊问题。 - After analyzing the classic 2-D and serial transportation systolic array architecture, a novel structure matrix multiplier based on 3-D square and serial-parallel mixed transportation was proposed.
在分析经典二维，串行心动结构矩阵乘法器的基础上，提出了基于三维的、串并行数据传输的新型结构。 - A constant time sorting processor array architecture with a reconfigurable bus system
一个带有可变结构总线的常数排序处理机阵列 - Realization of BP Algorithm in FPGA Based on Systolic Array Architecture
BP算法的脉动阵列结构在FPGA上的实现 - It adopts a new systolic array architecture, which can improve the speed by increasing the frequency without the size increased.
设计采用的新型心动阵列结构，可以在有效控制芯片面积的前提下，极大地提高运算频率，从而提高运算速度。 - Frame-Level Pipelined Array Architecture for Motion Estimation
基于帧级流水脉动阵列结构的运动估计电路 - On the VLSI Array Architecture for Real-time Image Matching
基于VLSI技术的实时图像匹配阵列结构的研究 - In this paper, we use a multiuser detection based on systolic array, this systolic architecture adaptively reconfigures the tap coefficient of the transversal filter, through comparing it with other detection, the conclusion is drawn that the detector has high performance.
本文采用了一种脉动阵列多用户检测器，它采用脉动阵列结构，能够自适应地调整横向滤波器的抽头系数，与其他检测器比较，它具有较好的性能。 - Second, it do research on the theory of Quality of Service, such as IntServ and DiffServ module, QoS protocols, QoS array techniques and QoS architecture.
对服务质量（QualityOfService，QoS）中的主要理论，如IntServ和DiffServ服务模型、QoS协议、QoS队列技术、QoS体系结构进行了探讨； - This paper describes the characteristics of a new ( Chebyshev Nonuniform Sampling CNS) model and the corresponding implementation schemes using Systolic array architecture This paper shows that the CNS model has the advantages of simplicity, regularity and fast reconstruction.
本文描述一种新的切匹雪夫非均匀抽样模式的特性和利用脉动阵列结构相应的实现方案。本文证明切匹雪夫非均匀抽样（CNS）模式具有简单、规则和快速重构的优点。 - To obtain the highest data reuse efficiency and minimum I/ O pin count while achieving 100% hardware efficiency, a systolic array and full pipeline architecture is adopted.
通过脉动阵列和全流水线的设计，达到最高的数据重用率、最小的I/O引脚数和100%的硬件计算效率。 - LEAP ( Loop Engine on Array Processors) is a new architecture that we promote to speed up execution of kernel loop.
循环阵列处理器（LoopEngineonArrayProcessors，LEAP）是我们提出的一种针对循环进行加速的全新体系结构模型。 - A Novel Systolic Linear Array Architecture for Partitioning Montgomery Modular Multiplication
分割式Montgomery模乘运算的线性高基心动阵列新结构 - A basic method for solving the problem of input data dependence and RAW dependence of inter-iteration in array architecture is also offered in this paper.
对于循环迭代间的输入数据相关和写后读相关，本文提出了在阵列结构上解决这些数据相关的基本思想。 - According to the character of the images, we proposed an ASIP array design based on RISC architecture for image denoise in the project.
本文依托图像实时处理项目，针对CCD图像的特点，提出了一种采用基于RISC架构的ASIP阵列处理机来进行降噪的方法。 - Based on the analysis of traditional fault-tolerant methods and existing bio-inspired fault-tolerant architecture, a novel bio-inspired self-organized computing array architecture is proposed in this paper. Firstly, we have studied the label-based bio-inspired computing array.
在分析传统容错结构和现有的仿生容错结构的基础上，本文提出了一种新的仿生自组织计算阵列体系结构。本文首先研究了基于标识的仿生自组织计算阵列体系结构。